The design of high speed microprocessors must be logically well-defined. The increased design complexity of leading-edge microprocessors and systems on a chip (SoC) is driving the industry to find better ways to implement the physical and logical designs of chips.
Using a computer layout generated as a blueprint, a number of basic CMOS transistor layers, contacts, and metal layers defining the elements and interconnections of the integrated circuit (IC) are created in silicon. This involves a combination of semiconductor processes namely depositing, masking, and etching. When combined, the layers form the IC with functions. Depending on the complexity of the chip, each circuit may involve multiple basic layers, multiple contacts, and multiple metal layers. This layer-patterns-release procedure is widely known as tape-out.
Following tape-out, for various reasons including design changes, modifications are subsequently required to delete logic elements as well as add logic elements and interconnections from the original design. When this occurs, an engineering change order (ECO) is generated to specifically document the desired changes. Bug fixes are also common. Therefore, integrated circuit designers put spare cells or spare gates in CMOS logic in pre-determined areas of the integrated circuit layouts. The spare gates are formed in arrays and can be used as spare logic for physical fixes requiring only higher level changes (e.g., metal only change) in the several layers of the chip. Having enough gate arrays in a design may determine if a bug fix is possible in a certain derivation of the design.
However, adding spare gates to a design has an associated cost. The spare gates take up space on the chip and consume power. Although spare gates do not function in the actual logic, the spare gates have their gates tied to high or low voltage. Thus current leakage occurs through the gates. As the number of spare gates increase on a chip, there may be significant power leakage.